Easy to use one window interface

Time to error

- Error Browser will pop up and allow viewing of errors while job is still running

Standard DRC Browsing capabilities

- By Cell/ By Rule

Error Waivers

- Persistent and loadable in subsequent runs

Graphic LVS Debug accelerates identification of complex LVS mismatches in chip designs

- Compares logical and physical design using a common schematic representation

- Guides navigation using design errors

- Can be launched with LVS debug environment, and graphical elements can be probed through the LVS debug environment

- All errors and warnings are easily navigated and show surrounding context

Error Tags

World view or detail view

Filter net, devices for better understanding of error

Drill down for more information on points of interest

etc

Limitation of current tools

- Static error report in batch mode, contain large data, difficult to understand

- Errors in text report hard to identify relationship

- User cannot actively query more information on points of interest

- Not allow easy navigation of the original design

Bind-key - Cadence Composor like

Locating shorts found in old-fashion LVS comparison report requires

- Additional manual work

- Additional LVS extraction and comparison runs

PVS approach facilitates one-pass short isolation for cell / block / full-chip designs

- Run time typically <10% of extraction time and scales up to 5x with 8 CPUs

- Start debugging while run is in progress as soon as first results are available