AGENDA |
Time | Topic | ||
08:30 - 09:00 | Registration Opens | ||
09:00 - 09:10 | Welcome Speech | ||
09:10 - 09:40 | Cadence SPB Business Strategy | ||
09:40 - 10:20 | The Big Trends with Success Stories | ||
10:20 - 10:50 | Break Time | ||
10:50 - 12:00 | Cadence Keynote | ||
12:00 - 13:10 | Lunch Break | ||
13:10 - 13:55 |
Track 1 OrCAD / Allegro |
Track 2 Sigrity |
Track 3 IC Packaging |
Circuit Design / Simulation Requirement & Solution 電路設計 / 驗證需求與解決方案 - Graser |
Cadence SI / PI / EMI Technologies Status and Roadmap Cadence SI / PI / EMI 技術現況與未來發展 - Cadence |
2.5D / 3D Design Solution - Graser Virtuoso - 3DEM Integration - Cadence |
|
13:55 - 14:40 |
OrCAD ERC - Cadence |
High-speed Serial Signal Design Analysis with CTLE - Customer |
Cadence Transistor-Level EMIR Solution - Graser |
14:40 - 15:00 | Break Time | ||
15:00 - 15:45 |
Increase Productivity and Quality by New Layout flow - Customer and Graser |
Comprehensive DDR4 Design Analysis Experience Sharing - Customer |
Smart Die / Package / PCB Planning and Optimization - Cadence |
15:45 - 16:30 |
Allegro New Products - DRC / DFM Checkers - Graser |
Potentially Power Delivery Network Issue in Simple Structs Design - Customer and Graser |
Package RLC Extraction and Assessment Solution - Cadence |
16:30 - 16:40 | Lucky Draw |